The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed.
One process where advances are concentrated is lithography—lithography generally involves the patterned exposure of a photosensitive layer on a target substrate so that portions of the layer can be selectively removed to provide a masking element on the substrate. The masking layer exposes underlying areas for selective processing such as by etching, material deposition, implantation and the like. Photolithography utilizes electromagnetic energy in the form of ultraviolet light for selective exposure of the resist. As an alternative to electromagnetic energy, charged particle beams have been used for high resolution lithographic resist exposure. In particular, electron beams have been used since the low mass of electrons allows relatively accurate control of an electron beam at relatively low power and relatively high speed. Electron beam lithography system is also an effective method to scale down the feature size. However, production-level wafer throughput by the current lithography systems is a challenge in large scale fabrication in the IC industry.
Accordingly, what needed are systems and methods for increasing the wafer throughput and saving the footprint for the lithography system.